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140 | #include "main.h"
static uint32_t SFC_ReadID(uint32_t *id)
{
uint32_t res;
SFC->CFG &= ~SFC_CFG_CMDTYPE_Msk;
SFC->CFG |= (1 << SFC_CFG_CMDWREN_Pos) |
(3 << SFC_CFG_CMDTYPE_Pos);
SFC->CMD = 0x90;
SFC->GO = 1;
while(SFC->GO);
SFC->CFG &= ~SFC_CFG_WREN_Msk;
*id = SFC->DATA;
if(SFC->IF & SFC_IF_ERR_Msk)
res = SFC_RES_ERR;
else if(SFC->IF & SFC_IF_TO_Msk)
res = SFC_RES_TO;
else
res = SFC_RES_OK;
return res;
}
static uint32_t SFC_ReadStatusRegister(uint8_t status_reg,uint8_t *data)
{
uint32_t res;
SFC->CFG &= ~SFC_CFG_CMDTYPE_Msk;
SFC->CFG |= (1 << SFC_CFG_CMDWREN_Pos) |
(1 << SFC_CFG_CMDTYPE_Pos);
SFC->CMD = status_reg;
SFC->GO = 1;
while(SFC->GO);
SFC->CFG &= ~SFC_CFG_WREN_Msk;
*data = SFC->DATA;
if(SFC->IF & SFC_IF_ERR_Msk)
res = SFC_RES_ERR;
else if(SFC->IF & SFC_IF_TO_Msk)
res = SFC_RES_TO;
else
res = SFC_RES_OK;
return res;
}
static uint32_t SFC_WriteStatusRegister(uint8_t status_reg,uint8_t status_reg1)
{
uint32_t res;
SFC->CFG &= ~SFC_CFG_CMDTYPE_Msk;
SFC->CFG |= (1 << SFC_CFG_WREN_Pos) | //write enable
(1 << SFC_CFG_CMDWREN_Pos) |
(6 << SFC_CFG_CMDTYPE_Pos);
SFC->CMD = 0x01;
SFC->DATA = (status_reg1 << 8) | status_reg;
SFC->GO = 1;
while(SFC->GO);
SFC->CFG &= ~SFC_CFG_WREN_Msk;
if(SFC->IF & SFC_IF_ERR_Msk)
res = SFC_RES_ERR;
else if(SFC->IF & SFC_IF_TO_Msk)
res = SFC_RES_TO;
else
res = SFC_RES_OK;
return res;
}
static uint32_t SFC_Enable_QuadSPI(void)
{
uint32_t res;
uint8_t status_reg;
uint8_t status_reg1;
res = SFC_ReadStatusRegister(0x05,&status_reg);
if(res != SFC_RES_OK)
return res;
res = SFC_ReadStatusRegister(0x35 ,&status_reg1);
if(res != SFC_RES_OK)
return res;
status_reg1 |= (1 << 1); //enable QuadSPI
res = SFC_WriteStatusRegister(status_reg,status_reg1);
return res;
}
void SFC_Config(uint8_t width)
{
SFC_InitStructure SFC_initStruct;
PORT_Init(PORTD, PIN5, PORTD_PIN5_FSPI_SCLK, 0);
PORT_Init(PORTD, PIN6, PORTD_PIN6_FSPI_SSEL, 0);
PORT_Init(PORTD, PIN8, PORTD_PIN8_FSPI_MOSI, 1);
PORT_Init(PORTD, PIN7, PORTD_PIN7_FSPI_MISO, 1);
PORT_Init(PORTD, PIN3, PORTD_PIN3_FSPI_DATA2, 1);
PORT_Init(PORTD, PIN4, PORTD_PIN4_FSPI_DATA3, 1);
switch (width)
{
case 1:
default:
SFC_initStruct.ClkDiv = SFC_CLKDIV_2;
SFC_initStruct.Cmd_Read = 0x03;
SFC_initStruct.Width_Read = SFC_RDWIDTH_1;
SFC_initStruct.Cmd_PageProgram = 0x02;
SFC_initStruct.Width_PageProgram = SFC_PPWIDTH_1;
break;
case 2:
SFC_initStruct.ClkDiv = SFC_CLKDIV_2;
SFC_initStruct.Cmd_Read = 0xBB;
SFC_initStruct.Width_Read = SFC_RDWIDTH_2;
SFC_initStruct.Cmd_PageProgram = 0x02;
SFC_initStruct.Width_PageProgram = SFC_PPWIDTH_1;
break;
case 4:
SFC_initStruct.ClkDiv = SFC_CLKDIV_4;
SFC_initStruct.Cmd_Read = 0xEB;
SFC_initStruct.Width_Read = SFC_RDWIDTH_4;
SFC_initStruct.Cmd_PageProgram = 0x32;
SFC_initStruct.Width_PageProgram = SFC_PPWIDTH_4;
break;
}
SFC_Init(&SFC_initStruct);
SFC_Enable_QuadSPI();
}
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